Phase-modulated continuous-wave (PMCW) radar is a promising radar topology that modulates a binary pseudo-random noise (PN) signal onto a fixed carrier frequency and determines the target distance from correlation. The PN signal’s bit rate sets the system’s RF bandwidth and range resolution and must be chosen accordingly high. This demands using frequency bands offering a large bandwidth, like the D-band, from 110 to 170 GHz. The research project associated with this thesis aims to develop a MIMO PMCW radar system operating at a center frequency of 140 GHz and a bandwidth of 25 GHz. This goal requires a technology combining millimeter-wave and high-speed digital circuits within the same IC, perfectly matched by the 22 nm FDSOI technology. The system must generate the PN signal on-chip, representing this thesis’s research focus. PN generators require high-speed flip-flops (FFs), of which multiples are proposed, realized, and compared. They belong to the dynamic true single-phase-clock (TSPC) or extended TSPC (E-TSPC) logic and can operate at high clock frequencies while consuming low energy. Three linear-feedback shift registers (LFSRs) employing the proposed FFs are presented to generate a fixed maximum-length sequence defined by the LFSRs’ feedback. The TSPC-based LFSR reaches a data rate of 41 Gb/s, and the E-TSPC-based version 45 Gb/s, which is the current state of the art. As opposed, an arbitrary sequence generator is presented, which can generate every binary sequence up to a fixed length. It is implemented as a mixed-signal IC, which comes at the cost of an increased circuit area and a reduced bit rate of 22.5 Gb/s. Both circuits can be extended by a proposed digital outer code generator that enables MIMO operation and can easily be scaled to feed multiple transmitter channels at negligible hardware cost. Finally, the baseband circuits are integrated into an overall transmitter, and their feasibility in the system is demonstrated by measurement.